`timescale 1ns/1ps

module nco_ask (
	input clk,    // Clock
	input rst_n,  // Asynchronous reset active low
	input [31:0] fcw,
	input din,
	input din_valid,
	input load,
	input [11:0] lut_data,
	output [14:0] lut_addr,
	output [11:0] out,
	output out_valid);

reg [11:0] out_reg;
reg out_valid_reg;
reg [31:0] phase_adder; //相位累加器
reg [31:0] fcw_reg; //频率控制字寄存器

wire [31:0] addr; //相位累加器2

reg [1:0] cdc_buf;
reg din_valid_bfd,din_bfd; //buffered

assign out = (fcw_reg != 0 && din_bfd && din_valid_bfd) ? out_reg : 0;
assign out_valid = (fcw_reg != 0 && din_valid_bfd) ? 1 : 0;
assign lut_addr = addr[31:17];
assign addr = phase_adder + fcw_reg;

always @(posedge clk or negedge rst_n) begin
	if(~rst_n) begin
		 out_reg <= 0;
		 out_valid_reg <= 0;
		 phase_adder <= 0;
		 fcw_reg <= 0;
	end else begin
		cdc_buf <= {din_valid , din};
		din_bfd <= cdc_buf[0];
		din_valid_bfd <= cdc_buf[1];
		phase_adder <= phase_adder + fcw_reg;
		out_reg <= lut_data;
		if(load) begin
			fcw_reg <= fcw;
		end
	end
end
endmodule